Neural-Networks-on-Silicon

Why we included this project

Researchers and students getting into AI hardware will find this a genuinely useful starting map: a hand-curated bibliography of the papers that defined neural network accelerators and AI chip architecture, organized by year and by the major systems conferences. Because the author is an active AI-chip researcher, the selections carry editorial judgment about which works actually moved the field, and each entry notes the institutions involved and what the paper contributes. It covers well-known landmarks such as DianNao, Eyeriss, and EIE as well as many lesser-cited works, so you can watch ideas about dataflow, sparsity, and near-threshold computing evolve across more than a decade of conference papers. Treat it as a reading guide rather than a deployable tool. The curation and chronological framing make it far easier to build context than digging through proceedings cold, which is why it works well as a graduate seminar syllabus or as a survey for an engineer scoping out the design space before starting a hardware project.