hls4ml

Why we included this project

hls4ml turns a trained neural network into FPGA firmware. You give it a model from Keras, PyTorch, or ONNX, and it produces high-level synthesis C++ that Vivado HLS or Intel HLS can compile into a bitstream and IP core. That makes microsecond-scale, low-power inference possible where a network round-trip would be too slow. It has been used in CERN's L1 trigger systems, quantum-computing control loops, fusion feedback, and satellite monitoring. For FPGA deployments where latency, resource usage, and power all matter, hls4ml gives you direct control over quantization and pruning, and lets you trade throughput against latency, so the final design.